View IDT5V925BI_4670869.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet idt5v925bqgi revision b january 21, 2011 1 ?2011 integrated device technology, inc. programmable lvcmos/lvttl clock generator IDT5V925BI general description the IDT5V925BI is a high-performance, low skew, low jitter phase-locked loop (pll) clock driver. it provides precise phase and frequency alignment of its clock outputs to an externally applied clock input or internal crystal oscillator. the IDT5V925BI has been specially designed to interface with gigabit ethernet and fast ethernet applications by providing a 125mhz clock from 25mhz input. it can also be programmed to provide output frequencies ranging from 3.125mhz to 160mhz with input frequencies ranging from 3.125mhz to 80mhz. the IDT5V925BI includes an internal rc filter that provides excellent jitter characteristics and eliminates the need for external components. when using the optional crystal input, the chip accepts a 10-30mhz fundamental mode crystal with a maximum equivalent series resistance of 50 ? . the on-chip crystal oscillator includes the feedback resistor and crystal capacitors (nominal load capacitance is 18pf). applications ? ethernet/fast ethernet ? router ? network switches ? san ? instrumentation features ? 3v to 3.6v operating voltage ? 3.125mhz to 160mhz output frequency range ? four programmable frequency lvcmos/lvttl outputs ? input from fundamental crystal oscillator or external source ? balanced drive outputs 12ma ? pll disable mode for low frequency testing ? select inputs (s[1:0]) for divide sele ction (multiply ratio of 2, 3, 4, 5, 6, 7 and 8) ? 5v tolerant inputs ? low output skew/jitter ? external pll feedback, internal loop filte r ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package q/n q0 q1 q2 optional crystal x1 x2 loop filter vco phase detector xtal osc fb clkin oe s0 s1 select mode vco divide 1/n 0 1 IDT5V925BI 16 lead qsop 0.194? x 0.236? x 0.058? package body q package top view pin assignment block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 s 1 s 0 gndq v ddq x 1 x 2 clkin fb gnd q 2 q 1 q 0 q/n gnd oe v dd
idt5v925bqgi revision b january 21, 2011 2 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. note 1: for best accuracy, use parallel resonant crystal specified for a load capacitance of 18pf. table 2. pin characteristics number name type description 1, 2 s1, s0 input pullup/ pulldown three level divider/mode select pins. float to mid. 3 gndq power ground supply for pll. 4v ddq power power supply for pll. 5x1 (1) input crystal oscillator input. connected to gnd if oscillator not required. 6x2 (1) output crystal oscillator output. leave unconnected for clock input. 7 clkin input clock input. 8 fb input pll feedback input which should be connec ted to q/n output pin only. pll locks onto positive edge of fb signal. 9oe input high-impedance output enable. when asse rted high, clock outputs are high impedance. 10, 15 gnd power ground supply for output buffers. 11 q/n output programmable divide-by-n clock output. 12, 13, 14 q0, q1, q2 output output at n*clkin frequency. 16 v dd power power supply for output buffers. symbol parameter test conditions minimum typical maximum units c in input capacitance clkin, fb, oe 4pf c pd power dissipation capacitance (per output) v dd = 3.6v 15 pf r pullup input pullup resistor 47 k ? r pulldown input pulldown resistor 47 k ? r out output impedance v dd = 3.3v0.3v 16 ?
idt5v925bqgi revision b january 21, 2011 3 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator function tables table 3a. function table note 1: operation in the specified clkin frequency range guarantee s that the vco will operate in the optimal range of 25mhz to 160mhz. operation with clkin outside specified frequency ran ges may result in invalid or out-of-lock outputs. note 2: q[2:0] are not allowed to be used as feedback. table 3b. divide selection table (1) note 1: h = high, m = medium, l = low. note 2: factory test mode: operation not specified. note 3: ethernet mode (use a 25mhz input frequency and q/n as feedback). note 4: test mode for low frequency testing. in this mode, cl kin bypasses the vco (vco powered down). frequency must be > 1mhz due to dynamic circuits in the frequency dividers. q[2:0] outputs are divided by 2 in test mode. output used for feedback allowable clkin range (mhz) (1, 2) output frequency relationships minimum maximum q/n q[2:0] q/n 25/n 160/n clkin clkin x n s1 s0 divide-by-n value mode l l factory test (2) lm 2 pll lh 3 pll ml 4 pll mm5 (3) (default) pll mh 6 pll hl 7 pll hm 8 pll h h 16 test (4)
idt5v925bqgi revision b january 21, 2011 4 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. operating conditions dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: h = high, m = medium, l = low item rating supply voltage to ground, v term -0.5v to +4.6v dc input voltage, v in -0.5v to +4.6v dc output voltage, v out -0.5 to v dd +0.5v maximum power dissipation, t a = 85 c 0.55w storage temperature, t stg -65 c to +150 c package thermal impedance, ja 72.3 c/w symbol description minimum typical maximum units v dd / v ddq power supply voltage 3.0 3.3 3.6 v t a operating temperature -40 +25 +85 c symbol parameter test conditions minimum typical maximum units i ddq quiescent supply current v dd = v ddq = 3.6v; clkin = 2.5mhz; s[1:0] = mm, oe = h, all outputs unloaded 24ma i dd static supply current v dd = v ddq = 3.6v; s[1:0] = mm, oe = h, all outputs unloaded 83 102 ma dynamic supply current v dd = v ddq = 3.6v, f out = 70mhz; s[1:0] = lm, oe = gnd, all outputs loaded with 50 ? to gnd 80 160 ma
idt5v925bqgi revision b january 21, 2011 5 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator table 4b. lvcmos/lvttl dc characteristics , v dd = 3.3v 0.3v, t a = -40c to 85c note: conditions apply unless otherwise specified. note 1: these inputs are normally wired to v dd, gnd, or unconnected. if the inpu ts are switched in real time, the function and timing of the outputs may glitch, and the pll may require an additio nal lock time before all the datasheet limits are achieved. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditions minimum typical maximum units v il input low voltage 0.8 v v ih input high voltage 2 v v ihh input high voltage s[1:0] 3-level input only v dd - 0.6 v v imm input mid voltage s[1:0 ] 3-level input only v dd /2 - 0.3 v dd /2 + 0.3 v v ill (1) input low voltage s[1:0] 3-level input only 0.6 v i in (1) input leakage current clkin, fb v in = v dd or gnd, v dd = max. -5 +5 a i 3 (1) 3-level input dc current s[1:0] v in = v dd, high level 200 a v in = v dd /2 , mid level -50 +50 a v in = gnd, low level -200 a i ih input high current v in = v dd -5 0.07 5 a v ol output low voltage i ol = 12ma 0.15 0.55 v v oh output high voltage i oh = -12ma 2.4 2.8 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 30 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
idt5v925bqgi revision b january 21, 2011 6 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator ac electrical characteristics table 6a. ac characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: jedec standard 65. note 1: guaranteed by design but not production tested. note 2: measured from v dd /2 of the input crossing point to the output at v dd /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v dd /2. table 6b. input timing requirements, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units t r / t f rise and fall time; note 1 0.8v to 2v 0.7 1.8 ns odc output duty cycle; note 1, 2 44 56 % t pd propagation delay; note 1, 2 clkin to fb 50 450 ps t sk(o) output-to-output skew; note 1, 3, 4 q[2:0] 110 ps q/n - q[2:0] 450 ps tjit(cc) cycle-to-cycle jitter; note 1, 3 300 ps f out output frequency 25 160 mhz symbol parameter test conditions minimum maximum units fosc crystal oscillator frequency 10 30 mhz f in input frequency 25/n 160/n mhz
idt5v925bqgi revision b january 21, 2011 7 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator parameter measurement information lvcmos output load ac test circuit cycle-to-cycle jitter propagation delay output skew input and output test waveforms scope qx lvcmos gnd v dd, v ddq v dd, v ddq 1.65v 0.15v -1.65v 0.15v ? ? ? ? v dd 2 v dd 2 v dd 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q/n, q[2:0] t pd v dd 2 v dd 2 q/n, q[2:0] clkin t sk(b) v dd 2 v dd 2 qx qy 2v v th = v cc /2 0v 1ns 3v 1ns 2v v th = v cc /2 0v t r t f v cc 0.8 0.8 v dd v dd /2 v dd /2
idt5v925bqgi revision b january 21, 2011 8 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator parameter measurement in formation, continued output duty cycle/pulse width/period applications information recommendations for unused input and output pins inputs: clkin input for applications not requiring the us e of a clock input, but using the crystal interface, the clkin input has to be connected to x2 (output of the crystal oscillator). see figure 3. crystal inputs for applications not requiring the us e of the crystal oscillator, x2 should be left floating and x1 and should be tied to ground. see figure 2. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. t period t pw t period odc = v dd 2 v dd 2 x 100% t pw q[2:0]
idt5v925bqgi revision b january 21, 2011 9 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator how to use the IDT5V925BI the IDT5V925BI is a general-purpose phase-locked loop (pll) that can be used as a zero delay buffer or a clock multiplier. it generates three outputs at the vco frequency and one output at the vco frequency divided by n, where n is determined by the mode/ frequency select input pins s0 and s1. the pll will adjust the vco frequency (within the limits of the fu nction table) to ensure that the input frequency equals the q/n frequency. the IDT5V925BI can accept two types of input signals. the first is a reference clock generated by another device on the board which needs to be reproduced with a minimal delay between the incoming clock and output. the second is an external crystal. when used in the first mode, the crystal input (x1) should be tied to ground and the crystal output (x2) should be left unconnected. by connecting q/n to fb (see figure 1 ), the IDT5V925BI not only becomes a zero delay buffer, but also a clock multiplier. with proper selection of s0 and s1, the q0?q2 outputs will generate two, three, or up to eight times the input clo ck frequency. make sure that the input and output frequency specifications are not violated (refer to function table). there are some appl ications where higher fan-out is required. these kinds of applications could be addressed by using the IDT5V925BI in conjunction with a clock buffer such as the 49fct3805. figure 2 shows how higher fan-out with different clock rates can be generated. figure 1 figure 2 by connecting one of the 49fct3505 outputs to the fb input of the IDT5V925BI, the propagation delay from clkin to the output of the 49fct3505 will be nearly zero. to ensure pll stability, only one 49fct3505 should be included between q/n and fb. the second way to drive the input of the IDT5V925BI is via an external crystal. when connecting an external crystal to pins 5 and 6, the x2 pin must be shorted to the clkin (pin 7) as shown in figure 3. to reduce the parasitic between the external crystal and the IDT5V925BI, it is recommended to connect the crystal as close as possible to the x1 and x2 pins. figure 3 one of the questions often asked is wh at is the accuracy of our clock generators? in applications wher e clock synthesizers are used, the terms frequency accuracy and frequency error are used interchangeably. here, frequency accuracy (or error) is based on two factors. one is the input frequency and the other is the multiplication factor. clock multipliers (or synthesizers) are governed by the equation: where ?m? is the feedback divide and ?n? is the reference divide. if the ratio of m/n is not an intege r, then the output frequency will not be an exact multiple of the input. on the other hand, if the ratio is a whole number, the output clock would be an exact multiple of the input. in the case of IDT5V925BI, since the reference divide (?n?) is ?1?, the equation is a strong function of the feedback divide (?m?). in addition, since the feedback is an integer, the output frequency error (or accuracy) is merely a function of how accurate the input is. for instance, IDT5V925BI could accept two forms of input, one from a crystal oscillator (see figure 1) and the other from a crystal (see figure 3). by using a 20mhz clock with a multiplication factor of 5 (with an accuracy of 30 parts per million), one can easily have three copies of 100mhz of clock with 30ppm of accuracy. frequency accuracy is defined by the following equation: accuracy = measured frequency ? nominal frequency x 10 6 nominary frequency where measured frequency is the average frequency over certain number of cycles (typically 10,000) and the nominal frequency is the desired frequency. fb clkin x 2 x 1 s 0 s 1 q/n q 0 q 1 q 2 5v925 5 copies of q/n 5 copies of q 49fct3805 fb clkin x 2 x 1 s 0 s 1 q [2:0] q/n ina inb 5v925 clkin x 2 x 1 s 0 s 1 q 0 q 1 q 2 q/n xtal osc 5v925 fb fout m n ---- - fin =
idt5v925bqgi revision b january 21, 2011 10 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator schematic examples figures 4a and 4b show an examples of IDT5V925BI application schematic. in figure 4a example, the device is operated at v dd = v ddq = 3.3v. the 18pf parallel reson ant 25mhz crystal is used. the load capacitance, c1 = 27pf and c2 = 27pf are recommended for frequency accuracy. depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specificatio ns can be used. this will required adjusting c1 and c2. in figure 4b example, the lvcmos clock reference input is used. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the IDT5V925BI provides separate power supplies to isolate from coupling into the internal pll. figure 4a. IDT5V925BI application schematic with crystal input reference r4 100 set logic input to '0' c5 10uf 1 8 p f please short the clkin pin and x2 pin for the crystal input option. ru1 1k r1 33 s1 rd2 1k r3 100 3.3v r2 33 lvcmos ru2 not install to logic input pins s2 /oe logic control input examples c8 10uf q/n vdd unused output can be left floating. there should no trace attached to unused output. device characterized with all outputs terminated. vddq=3.3v lvcmos vdd=3.3v c7 0.1uf c4 0.1uf vddq zo = 50 ohm rd1 not install vddq zo = 50 ohm c6 0.1uf xta l _i n x1 25mhz set logic input to '1' u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s1 s0 gndq vddq x1 x2 clkin fb /oe gnd q/n q0 q1 q2 gnd vdd vdd c1 27pf xtal_out c2 27pf q1 optional termination q0 blm18bb221sn1 ferrite bead 1 2 vdd to logic input pins 3.3v c3 0.1uf blm18bb221sn2 ferrite bead 1 2 q2
idt5v925bqgi revision b january 21, 2011 11 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator schematic examples, continued figure 4b. IDT5V925BI application schematic with lvcmos reference clock input in order to achieve the best possible filtering, it is recommended that the placement of the filter componen ts be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the ot her components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed fo r wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supply frequencies, it is re commended that component values be adjusted and if required, additi onal filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. zo = 50 ohm to logic input pins c6 0.1uf logic control input examples c7 0.1uf rd2 1k 3.3v c3 0.1uf blm18bb221sn2 ferrite bead 1 2 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s1 s0 gndq vddq x1 x2 clkin fb /oe gnd q/n q0 q1 q2 gnd vdd vddq unused output can be left floating. there should no trace attached to unused output. device characterized with all outputs terminated. v dd=3.3v ru1 1k set logic input to '1' r2 33 vdd c5 10uf zo = 50 ohm v ddq=3.3v r3 100 vddq to logic input pins blm18bb221sn1 ferrite bead 1 2 q0 q1 ru2 not install ro ~ 7 ohm q1 driv er_lvcmos s1 /oe q/n zo = 50 ohm lvcmos optional termination vdd vdd r1 33 r4 100 vdd lvcmos c8 10uf q2 rd1 not install set logic input to '0' 3.3v s2 r5 43 c4 0.1uf
idt5v925bqgi revision b january 21, 2011 12 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator power considerations this section provides information on power dissipa tion and junction temperature for the IDT5V925BI. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT5V925BI is the sum of the core power plus the power dissipation in the load(s). the foll owing is the power dissipation for v dd = 3.3v + 0.3v = 3.6v, which gives worst case results. the maximum current at 85c is as follows: i dd_max(static) = 102ma i ddq_max = 4ma c l = 5pf n = number of outputs c pd = 15pf core output power dissipation power (core) max = v dd_max * (i dd _max(static) + i ddq_max ) = 3.6v *(102ma + 4ma) = 382mw lvcmos output power dissipation output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.6v / [2 * (50 ? + 16 ? )] = 27.3ma power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 16 ? * (27.3ma) 2 = 11.9mw per output total power dissipation on the r out total power (r out ) = 11.9mw * 3 = 35.7mw dynamic power dissipation dynamic power dissipation at 160mhz total power (160mhz) = [(c pd + c l ) * n) * frequency * (v dd ) 2 ] = [(15pf + 5pf) * 3) * 160mhz * (3.6v) 2 ] = 124.4mw total power dissipation total power = power (core) + total power (r out ) + total power (160mhz) = 382mw + 35.7mw + 124.4mw = 542mw
idt5v925bqgi revision b january 21, 2011 13 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 72.3c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.542w * 72.3c/w = 124.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 16-lead qsop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 72.3c/w 64.4c/w 60.0c/w
idt5v925bqgi revision b january 21, 2011 14 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator reliability information table 8. ja vs. air flow table for a q suffix, 16-lead qsop ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 72.3c/w 64.4c/w 60.0c/w
idt5v925bqgi revision b january 21, 2011 15 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator package outline and package dimensions package outline - q suffix for 16 lead qsop table 9. package dimensions ref. document: idt pc/pcg package outline, dwg# psc-4040 jedec variation: ab all dimensions in inches symbol minimum nominal maximum n 16 a 0.061 0.064 .068 a1 0.004 0.006 0.010 a2 0.055 0.058 0.061 d 0.189 0.194 0.196 e 0.230 0.236 0.244 e1 0.150 0.155 0.157 p 0.274 0.282 p1 0.142 0.150 p2 0.175 basic e 0.025 basic x 0.010 0.018
idt5v925bqgi revision b january 21, 2011 16 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator ordering information table 10. ordering information note: parts that are ordered with an "g" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 5v925bqi idt5v925bqi 16 lead qsop tube -40 c to 85 c 5v925bqi8 idt5v925bqi 16 lead qsop 3000 tape & reel -40 c to 85 c 5v925bqgi idt5v925bqgi ?lead-free? 16 lead qsop tube -40 c to 85 c 5v925bqgi8 idt5v925bqgi ?lead-free? 16 lead qsop 3000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
idt5v925bqgi revision b january 21, 2011 17 ?2011 integrated device technology, inc. IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator revision history sheet rev table page description of change date b 8 10 applications for unused i/o pins applicat ion note - corrected input descriptions. deleted overdriving the xtal interface application note. 1/21/11
IDT5V925BI data sheet programmabl e lvcmos/lvttl clock generator disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is subj ect to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property righ ts of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of IDT5V925BI

	To Download IDT5V925BI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .